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Yosys
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Description

Name: Yosys Open SYnthesis Suite

Page: http://www.clifford.at/yosys/

Why include: Yosys is an open synthesis suite for Verilog RTL and the de-facto standard open synthesis solution due to its open backend design. Together with the existing Icarus Verilog and Verilator packages, inclusion would provide Solus with a robust toolkit for electronics design, making it a very attractive distro for engineers and hobbyists alike.

Open Source: Yes, GPL compatible

Repo: https://github.com/cliffordwolf/yosys.git

Latest release (0.8) tarball: https://github.com/YosysHQ/yosys/archive/yosys-0.8.tar.gz