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Name: Yosys Open SYnthesis Suite


Why include: Yosys is an open synthesis suite for Verilog RTL and the de-facto standard open synthesis solution due to its open backend design. Together with the existing Icarus Verilog and Verilator packages, inclusion would provide Solus with a robust toolkit for electronics design, making it a very attractive distro for engineers and hobbyists alike.

Open Source: Yes, GPL compatible


Latest release (0.8) tarball:

Event Timeline

paulsc created this task.Mar 3 2019, 9:03 PM
paulsc renamed this task from Package Request: Yosys to Yosys.Mar 3 2019, 9:06 PM
DataDrake triaged this task as Normal priority.Mar 3 2019, 9:37 PM
DataDrake moved this task from Backlog to Accepted For Inclusion on the Package Requests board.