Page MenuHomeSolus

Closed, ResolvedPublic


Name: Verilator
Latest Version: 4.002 (Sept 16. 2018)
Official Tarball:

Verilator is a high speed verilog to C++ / SystemC converter. It allows simulation of HDL designs much faster (in some cases up to 90x faster) than the currently included Icarus Verilog, and most importantly supports SystemVerilog where iverilog does not. It is currently packaged by Debian and Ubuntu.

Verilator is open-source under LGPLv3.

I am willing to create the package for Verilator, I have already made a prototype package that needs testing.

Event Timeline

memchk created this task.Sep 28 2018, 4:07 PM
memchk claimed this task.Oct 2 2018, 10:37 PM

Update: I have a working and tested package ready for Verilator as soon as this is approved for inclusion.

DataDrake triaged this task as Normal priority.Oct 2 2018, 10:52 PM
DataDrake moved this task from Backlog to Accepted For Inclusion on the Package Requests board.