Verilator is a high speed verilog to C++ / SystemC converter. It allows simulation of HDL designs much faster (in some cases up to 90x faster) than the currently included Icarus Verilog, and most importantly supports SystemVerilog where iverilog does not. It is currently packaged by Debian and Ubuntu.
Verilator is open-source under LGPLv3.
I am willing to create the package for Verilator, I have already made a prototype package that needs testing.